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Refer to Xilinx's product guide for this core to learn more about using it, or to Macronix's datasheet for the flash device to learn how to implement a custom controller. Xilinx's AXI Quad SPI IP core can be used to read/write the flash in a MicroBlaze design. The implementation of this protocol is outside the scope of this document. The contents of the memory can be manipulated by issuing certain commands on the SPI bus. It is possible to automatically generate this bootloader, roll it into the bitstream, and then program the bitstream and large MicroBlaze program into the Quad SPI Flash using Xilinx SDK. These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory.

A common use for this extra memory is to store MicroBlaze programs too big to fit in the onboard block memory. A Spartan-7 25T configuration file requires 9,935,224 bits of memory, leaving about 69% of the flash device (or ~2.8 MB) available for user data. The FPGA will automatically read a configuration file from this device at power on. Quad-SPI programming can be performed using Vivado's Hardware Manager.įPGA Configuration files can be written to the Quad-SPI Flash (Macronix part number MX25元233F). Programming files stored in the flash device will remain until they are overwritten, regardless of power-cycle events. After the flash device has been programmed, it will automatically configure the FPGA at any subsequent power-on event. First, the FPGA is programmed with a circuit that can program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). When programming a non-volatile flash device, a bitstream file is transferred to the flash in a two-step process. To that effect, a configuration file needs to first be written to the flash.

The blank FPGA takes the role of master and reads the configuration file out of the flash device upon power-up. This configuration mode is called Master SPI. Since the FPGA's memory on the Cmod S7 is volatile, it relies on the Quad-SPI flash memory to store the configuration between power cycles. The following sections provide greater detail about programming the Cmod S7 using the different methods available. For more information on how to do this, consult the Xilinx documentation for the toolset being used.Īfter successful programming, the FPGA will cause the “DONE” LED to illuminate.

Bitstream compression can be enabled within the Xilinx tools to occur during generation, and is enabled by default in Digilent's master XDC file for the Cmod S7. Depending on design complexity, compression ratios of 10x can be achieved. The time it takes to program the Cmod S7 can be decreased by compressing the bitstream before programming, and then allowing the FPGA to decompress the bitstream itself during configuration. This data defines the FPGA's logic functions and circuit connections, and it remains valid until it is erased by removing board power, or by writing a new configuration file using the JTAG port.Ī Spartan-7 25T bitstream is typically 9,935,224 bits.

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The Vivado software from Xilinx can create bitstreams from VHDL, Verilog®, or block-level designs.īitstreams are stored in volatile memory cells within the FPGA. The FPGA configuration data is stored in files called bitstreams that have the.

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